View LTC2992_9030998.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt c2992 1 rev a for more information www.analog.com document feedback typical application features description dual wide range power monitor the lt c ? 2992 is a rail-to-rail system monitor that mea - sures current, voltage, and power of two supplies. it features an operating range of 2.7v to 100v and includes a shunt regulator for supplies above 100v. the voltage measurement range of 0v to 100v is independent of the input supply. two adcs simultaneously measure each supply?s current. a third adc monitors the input voltages and four auxiliary external voltages. each supply ?s current and power is added for total system consumption. mini - mum and maximum values are stored and an overrange alert with programmable thresholds minimizes the need for software polling. data is reported via a standard i 2 c interface. shutdown mode reduces current consumption to 25a typically. the LTC2992 i 2 c interface includes separate data input and output pins for use with standard or opto-isolated i 2 c connections. the LTC2992-1 has an inverted data output for use with inverting opto-isolator configurations. dual wide range power monitor adc error (gpio) applications n rail-to-rail input range: 0v to 100v n wide input supply range: 2.7v to 100v n measures current, voltage, and power n shunt regulator for supplies >100v n 8-/12-bit adcs with less than 0.3% total unad- justed error n four general purpose inputs/outputs configurable as adc inputs n continuous scan and snapshot modes n stores minimum and maximum measurements n alerts when alarm thresholds exceeded n shutdown mode with i q < 50a n split sda pin eases opto-isolation n available in 16-lead 4mm 3mm dfn and msop packages n telecom infrastructure n industrial equipment n automotive n computer systems and servers all registered trademarks and trademarks are the property of their respective owners. v dd LTC2992 sdai sdao scl gpio4 gpio1 gpio2 v in1 3v to 100v i 2 c interface v in2 0v to 100v 0.01 alert 2992 ta01a sense2 + sense2 ? sense1 + sense1 ? 0.01 0.1f adr0 adr1 gnd intv cc gpio3 dataready measured voltage 2 measured voltage 1 v out1 v out2 12-bit mode typical code 0 1024 2048 3072 4096 ?0.50 ?0.25 0 0.25 0.50 adc error (%) 2992 ta01b max error
lt c2992 2 rev a for more information www.analog.com pin configuration absolute maximum ratings supply voltages v dd ...................................................... ? 0.3v to 100v intv cc (note 3) ..... ? 0.3v to lesser of 5.8v , v dd + 0.3v analog input voltages sensen + , sensen ? .................................? 1v to 100v sensen + to sensen ? ..................................? 1v to 1v ad r0 , ad r1 ............................................ ? 0.3v to 7v gpio1-4 ................................................... ? 0.3v to 7v digital input/output voltages scl, sdai (note 4) ............................... ? 0.3v to 5.9v sdao, sdao , gpio1-4 ............................. ? 0.3v to 7v (notes 1, 2) LTC2992 LTC2992 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 sense2 ? sense2 + gpio2 gpio4 gnd sdao sdai scl sense1 ? sense1 + gpio1 gpio3 adr1 adr0 intv cc v dd top view de package 16-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 43c/w, jc = 5.5c/w exposed pad (pin 17) pcb gnd connection is optional 1 2 3 4 5 6 7 8 sense1 ? sense1 + gpio1 gpio3 adr1 adr0 intv cc v dd 16 15 14 13 12 11 10 9 sense2 ? sense2 + gpio2 gpio4 gnd sdao sdai scl top view ms package 16-lead plastic msop t jmax = 150c, ja = 120c/w, jc = 21c/w LTC2992-1 LTC2992-1 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 sense2 ? sense2 + gpio2 gpio4 gnd sdao sdai scl sense1 ? sense1 + gpio1 gpio3 adr1 adr0 intv cc v dd top view de package 16-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 43c/w, jc = 5.5c/w exposed pad (pin 17) pcb gnd connection is optional 1 2 3 4 5 6 7 8 sense1 ? sense1 + gpio1 gpio3 adr1 adr0 intv cc v dd 16 15 14 13 12 11 10 9 sense2 ? sense2 + gpio2 gpio4 gnd sdao sdai scl top view ms package 16-lead plastic msop t jmax = 150c, ja = 120c/w, jc = 21c/w average pin currents intv cc .............................................. ? 10ma to 35ma scl, sdai ............................................................ 5ma sdao, sdao , gpio1-4 ....................................... 20ma operating junction temperature range lt c2992 c ................................................ 0c to 70 c lt c2992 i ............................................. ? 40 c to 85 c lt c2992 h .......................................... ? 40 c to 125 c storage temperature range .................. ? 65 c to 150 c lead temperature (soldering, 10sec) ms package only .............................................. 300 c
lt c2992 3 rev a for more information www.analog.com order information electrical characteristics symbol parameter conditions min typ max units supplies v dd v dd input supply voltage l 3 100 v v cc intv cc input supply voltage l 2.7 5.8 v i dd v dd supply current v dd = 48v, intv cc open shutdown l l 1.2 25 1.6 50 ma a i cc intv cc supply current intv cc = v dd = 5v shutdown l l 1.0 25 1.4 50 ma a v cc(ldo) intv cc linear regulator voltage 8v < v dd < 100v i load = 0ma l 4.6 5 5.4 v ?v cc(ldo) intv cc linear regulator load regulation 8v < v dd < 100v i load = 0ma to 10ma l 100 250 mv v ccz shunt regulator voltage at intv cc v dd = 48v, i cc = 1.5ma l 5.8 6.2 6.7 v ?v ccz shunt regulator load regulation v dd = 48v, i cc = 1.5ma to 35ma l 250 mv v cc(uvl) intv cc supply undervoltage lockout intv cc rising, v dd = intv cc l 2.2 2.5 2.69 v v dd(uvl) v dd supply undervoltage lockout v dd rising, intv cc open l 2.4 2.7 3 v v cci2c(rst) intv cc i 2 c logic reset intv cc falling, v dd = intv cc l 1.7 2.1 v v ddi2c(rst) v dd i 2 c logic reset v dd falling, intv cc open l 1.7 2.1 v sense inputs i sense + (hi) 48v sense + input current sense + , sense ? , v dd = 48v shutdown l l 120 170 2 a a i sense ? (hi) 48v sense ? input current sense + , sense ? , v dd = 48v shutdown l l 20 1 a a the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v dd is from 3v to 100v unless otherwise noted. (note 2) tube tape and reel part marking* package description temperature range LTC2992cde#pbf LTC2992cde#trpbf 2992 16-lead (4mm 3mm) plastic dfn 0c to 70c LTC2992ide#pbf LTC2992ide#trpbf 2992 16-lead (4mm 3mm) plastic dfn ?40c to 85c LTC2992hde#pbf LTC2992hde#trpbf 2992 16-lead (4mm 3mm) plastic dfn ?40c to 125c LTC2992cde-1#pbf LTC2992cde-1#trpbf 29921 16-lead (4mm 3mm) plastic dfn 0c to 70c LTC2992ide-1#pbf LTC2992ide-1#trpbf 29921 16-lead (4mm 3mm) plastic dfn ?40c to 85c LTC2992hde-1#pbf LTC2992hde-1#trpbf 29921 16-lead (4mm 3mm) plastic dfn ?40c to 125c LTC2992cms#pbf LTC2992cms#trpbf 2992 16-lead plastic msop 0c to 70c LTC2992ims#pbf LTC2992ims#trpbf 2992 16-lead plastic msop ?40c to 85c LTC2992hms#pbf LTC2992hms#trpbf 2992 16-lead plastic msop ?40c to 125c LTC2992cms-1#pbf LTC2992cms-1#trpbf 29921 16-lead plastic msop 0c to 70c LTC2992ims-1#pbf LTC2992ims-1#trpbf 29921 16-lead plastic msop ?40c to 85c LTC2992hms-1#pbf LTC2992hms-1#trpbf 29921 16-lead plastic msop ?40c to 125c consult adi marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http://www.linear.com/product/LTC2992#orderinfo
lt c2992 4 rev a for more information www.analog.com symbol parameter conditions min typ max units i sense + (lo) 0v sense + source current sense + , sense ? = 0v, v dd = 48v shutdown l l ?10 ?1 a a i sense ? (lo) 0v sense ? source current sense + , sense ? = 0v, v dd = 48v shutdown l l ?5 ?1 a a adc res resolution (no missing codes) (note 5) nadc[7] = 1 nadc[7] = 0 l l 8 12 bits bits v fs full-scale voltage ?sense (note 6) sense + gpio l l l 50.9 102 2.042 51.2 102.4 2.048 51.5 102.8 2.054 mv v v lsb lsb step size 8-bit mode ?sense sense + gpio 200 400 8 v mv mv lsb step size 12-bit mode ?sense sense + gpio 12.5 25 0.5 v mv mv tue total unadjusted error (note 7) 8-bit mode ?sense sense + gpio l l l 0.8 0.8 0.8 % % % total unadjusted error 12-bit mode ?sense sense + gpio l l l 0.6 0.4 0.3 % % % v os offset error 8-bit mode ?sense, sense + , gpio l 1 lsb offset error 12-bit mode ?sense (c-, i-grade) ?sense (h-grade) sense + gpio l l l l 2.1 3.1 1.5 1.1 lsb lsb lsb lsb inl integral nonlinearity 8-bit mode ?sense, sense + , gpio l 1 lsb integral nonlinearity 12-bit mode ?sense sense + , gpio l l 3.5 2 lsb lsb t transition noise ?sense sense + gpio 0.5 0.3 5 v rms mv rms v rms t conv conversion time (snapshot mode) 8-bit mode ?sense sense + , gpio l l 3.9 0.97 4.1 1.02 4.3 1.08 ms ms conversion time (snapshot mode) 12-bit mode ?sense sense + , gpio l l 62.4 15.6 65.6 16.4 68.8 17.2 ms ms gpio v gpio(th) gpio pin input threshold v gpio rising l 1.13 1.23 1.33 v v gpio(ol) gpio pin output low voltage i gpio = 8ma l 0.15 0.4 v i gpio gpio pin input current v dd = 48v, gpio = 3v l 0 1 a i 2 c interface (v dd = 48v) v adr(h) adr0, adr1 input high threshold l 1.8 2.4 2.7 v v adr(l) adr0, adr1 input low threshold l 0.3 0.6 0.9 v i adr(in) adr0, adr1 input current adr0, adr1 = 0v, 3v l 13 a i adr(in,z) allowable leakage when open l 7 a electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v dd is from 3v to 100v unless otherwise noted. (note 2)
lt c2992 5 rev a for more information www.analog.com note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive. all voltages are referenced to ground, unless otherwise noted. note 3: an internal shunt regulator limits the intv cc pin to a minimum of 5.8v. driving this pin to voltages beyond 5.8v may damage the part. this pin can be safely tied to higher voltages through a resistor that limits the current below 35ma. symbol parameter conditions min typ max units v od(ol) sdao, sdao , output low voltage i sdao , i sdao = 8ma l 0.15 0.4 v i sda,scl(in) sdai, sdao, sdao , scl leakage current sdai, sdao, sdao, scl = 5v l 0 1 a v sda,scl(th) sdai, scl input threshold l 1.5 1.8 2.1 v v sda,scl(cl) sdai, scl clamp voltage i sdai , i scl = 0.5ma, 5ma l 5.9 6.9 v i 2 c interface timing f scl(max) maximum scl clock frequency l 400 khz t low scl low period l 0.65 1.3 s t high scl high period l 50 600 ns t buf(min) bus free time between stop/start condition l 0.12 1.3 s t hd, sta(min) hold time after (repeated) start condition l 140 600 ns t su, sta(min) repeated start condition setup time l 30 600 ns t su, sto(min) stop condition setup time l 30 600 ns t hd, dati(min) data hold time input l ?100 0 ns t hd, dato(min) data hold time output l 300 600 900 ns t su, dat(min) data setup time l 30 100 ns t sp(max) maximum suppressed spike pulse width l 50 110 250 ns t rst stuck bus reset time scl or sdai held low l 25 33 ms c x scl, sdai input capacitance (note 5) 5 10 pf note 4: internal clamps limit the scl and sdai pins to a minimum of 5.9v. driving these pins to voltages beyond the clamp may damage the part. the pins can be safely tied to higher voltages through resistors that limit the current below 5ma. note 5: guaranteed by design and not subjected to test. note 6: ?sense is defined as v sense + ? v sense ? note 7: tue is the maximum adc error for any code expressed as a percentage of full-scale. electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v dd is from 3v to 100v unless otherwise noted. (note 2)
lt c2992 6 rev a for more information www.analog.com typical performance characteristics v dd supply current intv cc supply current intv cc load regulation intv cc line regulation intv cc shunt regulator load regulation sense input current adr voltage with current source or sink scl/sdai loaded clamp voltage vs load current gpio, sdao, sdao loaded output low voltage vs load current v dd supply voltage (v) 0 20 40 60 80 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 intv cc output voltage (v) 2992 g04 i adr (a) ?10 ?5 0 5 10 0 0.5 1.0 1.5 2.0 2.5 3.0 v adr (v) 2992 g07 i load (ma) 0.01 0.1 1 10 5.80 5.90 6.00 6.10 6.20 6.30 6.40 v sda,scl(cl) (v) 2992 g08 i od (ma) 0 2 4 6 8 10 0 0.1 0.2 0.3 0.4 v od(ol) (v) 2992 g09 load current (ma) 0 2 4 6 8 10 4.8 4.9 5.0 5.1 5.2 intv cc voltage (v) 2992 g03 normal shutdown v dd supply voltage (v) 0 20 40 60 80 100 0.8 1.0 1.2 1.4 18 22 26 30 supply current (ma) shutdown current (a) 2992 g01 normal shutdown intv cc supply voltage (v) 2 3 4 5 6 0.8 1.0 1.2 1.4 15 25 35 45 supply current (ma) shutdown current (a) 2992 g02 intv cc shunt current (ma) 0 10 20 30 40 6.10 6.15 6.20 6.25 6.30 intv cc voltage (v) 2992 g05 sense + sense ? sense voltage (v) 0 20 40 60 80 100 ?50 0 50 100 150 200 250 sense current (a) 2992 g06
lt c2992 7 rev a for more information www.analog.com typical performance characteristics adc error (gpio) adc integral nonlinearity (gpio) adc differential nonlinearity (gpio) adc error (?sense) adc integral nonlinearity (?sense) adc differential nonlinearity (?sense) adc input signal attenuation (gpio) adc input signal attenuation (gpio, low frequencies) adc input signal attenuation (?sense) frequency (hz) 0 60 120 180 240 ?80 ?60 ?40 ?20 0 rejection (db) 2992 g17 max error typical 12?bit mode code 0 1024 2048 3072 4096 ?0.50 ?0.25 0 0.25 0.50 adc error (%) 2992 g10 code 0 1024 2048 3072 4096 ?0.3 ?0.2 ?0.1 0.0 0.1 0.2 0.3 adc inl (lsb) 2992 g11 12?bit mode code 0 1024 2048 3072 4096 ?0.3 ?0.2 ?0.1 0.0 0.1 0.2 0.3 adc dnl (lsb) 2992 g12 12?bit mode max error 12?bit mode typical code 0 1024 2048 3072 4096 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 adc error (%) 2992 g13 code 0 1024 2048 3072 4096 ?2.0 ?1.0 0 1.0 2.0 adc inl (lsb) 2992 g14 12?bit mode code 0 1024 2048 3072 4096 ?1.0 ?0.5 0 0.5 1.0 adc dnl (lsb) 2992 g15 12?bit mode frequency (khz) ?100 ?80 ?60 ?40 ?20 0 rejection (db) 2992 g16 0 62.5 125 187.5 250 frequency (khz) ?100 ?80 ?60 ?40 ?20 0 rejection (db) 2992 g18 0 62.5 125 187.5 250
lt c2992 8 rev a for more information www.analog.com pin functions adr1, adr0: i 2 c device address inputs. connecting these pins to intv cc , gnd or leaving the pins open configures one of nine possible addresses. see table 3 in applications information section for details. exposed pad : exposed pad may be left open or connected to device ground. for best thermal performance, connect to a copper plane with an array of vias. gnd: device ground. gpio1, gpio2: general purpose input/output (open drain). configurable to general purpose output, logic in - put, or data converter input. tie to ground if unused. see table 18 in applications information section for details. gpio3: general purpose input/output (open drain). configurable to general purpose output, logic input, data converter input or data ready signal ( dataready). as dataready , it is latched low or pulses low for 16s or 128s when any of the adc? s data becomes available. tie to ground if unused. see table 18 in applications informa - tion section for details. gpio4: general purpose input/output (open drain). configurable to general purpose output, logic input, data converter input or smbus alert ( alert). as alert, it is pulled to ground when a fault occurs to alert the host con - troller. a fault alert is enabled by setting the corresponding bit in the alert registers as shown in tables 7, 11, 13 and 15. tie to ground if unused. see tables 18 and 19 in applications information section for details. intv cc : internal low voltage supply input/output. this pin is used to power internal circuitry. it can be configured as a direct input for a low voltage supply, as linear regula - tor from a higher voltage supply connected to v dd , or as a shunt regulator. connect this pin directly to a 2.7v to 5.8v supply if available. when intv cc is powered from an external supply, connect the v dd pin to intv cc . if v dd is connected to a 8v to 100v supply, intv cc becomes the 5v output of an internal series regulator that can supply up to 10ma to external circuitry. for even higher supply voltages or if a floating topology is desired, intv cc can be used as a 6.2v shunt regulator. connect the supply to typical performance characteristics adc input signal attenuation (?sense, low frequencies) current sense amplifier offset drift over temperature current sense amplifier offset drift over input common mode frequency (hz) 0 60 120 180 240 ?80 ?60 ?40 ?20 0 rejection (db) 2992 g19 calibration on calibration off initial calibration done at v cm = 48v no calibration thereafter 12?bit mode common mode voltage (v) 0 25 50 75 100 ?2 0 2 4 6 8 10 offset drift (lsb) 2992 g21 calibration on calibration off initial calibration done at 25c no calibration thereafter 12?bit mode temperature (c) ?50 ?25 0 25 50 75 100 125 ?25 ?15 ?5 5 15 25 offset drift (lsb) 2992 g20
lt c2992 9 rev a for more information www.analog.com pin functions intv cc through a resistor or current source that limits the current to less than 35ma . an undervoltage lockout circuit disables the adc when the voltage at this pin drops below 2.5v. connect a bypass capacitor of 0.1f or greater from this pin to ground. if an external load is present, for loop stability, use a bypass capacitor of 1f or greater. see flexible power supply section. scl: i 2 c bus clock input. data at the sdai pin is shifted in or out on rising edges of scl. this pin is driven by an open-collector output from a master controller. an external pull-up resistor or current source is required and can be placed between scl and v dd or intv cc . the voltage at scl is internally clamped to 6.3v typically. sdai: i 2 c bus data input. used for shifting in address, command or data bits. this pin is driven by an open- collector output from a master controller. an external pull-up resistor or current source is required and can be placed between sdai and v dd or intv cc . the voltage at sdai is internally clamped to 6.3v typically. tie to sdao for normal i 2 c operation. sdao (LTC2992 only): i 2 c bus data output. open-drain output used for sending data back to the master controller or acknowledging a write operation. an external pull-up resistor or current source is required. tie to sdai for normal i 2 c operation. sdao (LTC2992-1 only): inverted i 2 c bus data output. open-drain output used for sending data back to the master controller or acknowledging a write operation. data is inverted for convenience of opto-isolation. an external pull-up resistor or current source is required. the LTC2992-1 cannot be used in nonisolated i 2 c applications without additional components. sense1 + , sense2 + : supply voltage and current sense input. used as a voltage supply and current sense input for internal current sense amplifier. the voltage at this pin is monitored by the onboard adc with a full-scale input range of 102.4v. see figure 19 for recommended kelvin connection. sense1 ? , sense2 ? : current sense input. connect an external sense resistor between sense + and sense ? . the differential voltage between sense + and sense ? is monitored by the onboard adc with a full-scale sense voltage of 51.2mv . tie both sense ? and sense + together to a voltage between 0v and 100v if current measurement is unused. v dd : high voltage supply input. this pin powers an internal series regulator with input voltages ranging from 3v to 100v and produces 5v at intv cc when v dd is above 8v. connect a bypass capacitor of 0.1f or greater from this pin to ground if external load is present on the intv cc pin. see flexible power supply section.
lt c2992 10 rev a for more information www.analog.com functional diagram timing diagram t su, dat t su, sto t su , sta t buf t hd, sta t sp t sp t hd, dato, t hd, dati t hd, sta start condition stop condition repeated start condition repeated start condition 2992 td sda scl sense1 + sense1 ? v ref 2.048v 6.3v sense2 ? sense2 + 735k v dd gnd iadc1 iadc2 2992 fd vadc intv cc 6.2v 5v ldo ? + 40x ? + 40x 1 2 16 15 8 7 12 3 14 4 13 735k 15k 15k decoder adr1 sdao (LTC2992) sdao (LTC2992-1) adr0 scl sdai s1 s2 g1 g2 g3 g4 i1 + i2 p1 + p2 i2 p2 i1 p1 12 12 12 i 2 c 1.23v gpio1 gpio2 gpio3 gpio4 6.3v ? + 10 9 6 5 11 4
lt c2992 11 rev a for more information www.analog.com operation the LTC2992 accurately monitors current, voltage and power of two 0v to 100v supplies. an internal linear regulator allows the LTC2992 to operate directly from a 3v to 100v rail, or from an external supply voltage between 2.7v and 5.8v. quiescent current is less than 1.6ma in normal operation. enabling shutdown mode via the i 2 c interface reduces the quiescent current to below 50a. there are three onboard 8-/12-bit adcs as shown in the functional diagram. each supply?s load current is mea - sured with an external current sense resistor connected between sense + and sense ? . internal amplifiers gain up the voltage drop across the sense resistor for monitoring by the iadcs (full-scale 51.2mv ). vadc is used for voltage measurements and its input is selectively connected to sense1 + , sense2 + (full-scale 102.4v) or any of the four gpio pins (full-scale 2.048v). each conversion takes 33ms for the iadcs and 16ms for the vadc in 12-bit mode. the conversion time can be shortened by a factor of 16 when 8-bit mode is selected. the adcs can be configured to run continuously (continu - ous scan) or on demand (snapshot mode). in continuous scan mode, the vadc measures selected voltages of the six inputs in round robin fashion. see the applications information section for more details. status bits in the adc status register signal new conversion results from the adcs have been written into onboard registers. the gpio1 to gpio4 pins are also general purpose inputs or general purpose open-drain outputs. in addition, gpio3 may be configured as dataready output while gpio4 is also an smbus alert ( alert) output. dataready in - dicates availability of the most recent conversion results from any of the adcs while alert indicates one or more faults have occurred. onboard memory stores the minimum and maximum values for each adc measurement and calculates power data by digitally multiplying the stored current and voltage data. when the adc measured value falls outside its pro - grammed window thresholds, a fault event is logged and the alert (gpio4) may optionally pull low. the LTC2992 also calculates the total current and power consumption of the two monitored supplies. the LTC2992 includes an i 2 c interface to access the onboard data registers and to program the alert thresh - old, configuration and control registers. two three-state pins, ad r1 and adr0 , are decoded to allow nine device addresses (see table 3). the sda pin is split into sdai (input) and sdao (output, LTC2992 ) or sdao (output, LTC2992 -1) to facilitate opto-isolation. tie sdai and sdao together for normal, nonisolated i 2 c operation.
lt c2992 12 rev a for more information www.analog.com the LTC2992 offers a compact and complete solution to monitor power from two supply rails in high side and/or low side current sensing applications. with an input com - mon mode range of 0v to 100v and a wide input supply operating voltage range from 2.7v to 100v, this device is ideal for a wide variety of power management applications including automotive, industrial and telecom infrastructure. the basic application circuit shown in figure 1 provides monitoring of high side currents (5.12a/ 10.24a full-scale), input voltages (102.4v full-scale) and two external volt - ages (2.048v full-scale), all using internal 12-bit adcs. data converters the LTC2992 features three ? a/d converters (adc) that can be configured to 8- or 12-bit. the ? architec - ture inherently averages input signals and noise during the measurement period. two adcs (ia dc1 and iadc2) monitor the differential voltages between sense + and sense ? (?sense) with 51.2mv full-scale to allow accurate measurement of load currents across low value shunt resistors. the third adc (vadc) monitors two sense + and four gpio pins with full-scale of 102.4v for sense + and 2.048v for gpio. the supply voltage data are derived from sense1 + and sense2 + or gpio1 and gpio2 depending on the external application circuit. sen se1 + and sense2 + are selected by default as these are normally connected to the supply voltages. in negative supply voltage systems, the supply voltages can be measured through external resistive divid - applications information ers connected to the gpio1 and gpio2 pins. see flexible power supply section for details. the operation and conversion sequence of the adcs, mul - tiplier operand and vadc input selections are controlled by the settings in the ctrla register as shown in table 1. the timing sequence for some of these configurations are shown in figure 2 (2a to 2f). the timing diagram shown in figure 2a illustrates the conversion sequence in the default configuration (ctrla [7:0 ]=0x 00). upon power-up (t 1 ), the iadcs will always measure their corresponding current sense amplifier?s offset (calibration) and then the load current (?sense1 /2). meanwhile, vadc begins mea - surement of sense1 + , sense2 + , gpio1, gpio2, gpio3 and gpio4 successively. at t 3 a new iadc conversion begins. to generate power, the most recent voltage data (s1 at t 2 , s2 at t 3 ) from vadc is stored in a latch as an operand to the adder as shown in figure 3. imod1 represents iadc1?s modulator which converts the load current into a 1-bit data stream. each 1 in the bitstream adds to the accumulators the voltage data such that they contain the power values i1 s1 and i2 s2 at the end of the iadc conversions at t 5 . voltage latch content is then updated to the corresponding data registers. i1 is added to i2 to generate total current and p1 is added to p2 to generate total power. in the summing process, the least significant bit of the results are truncated. consequently, the summing results need to be shifted one bit to the left to restore the correct quantity. note that the figure 1. dual high side power monitor v dd LTC2992 sdai sdao scl sda scl gpio3 gpio1 gpio2 v in1 3v to 100v v in2 0v to 100v alert v out1 5a 3.3v v dd p gnd r1 2k r2 2k r3 2k r4 2k v out2 10a 2992 f01 sense2 + sense2 ? sense1 + sense1 ? r sense1 0.01 r sense2 0.005 0.1f adr0 adr1 gnd intv cc gpio4 int1 int0 dataready measured voltage 2 measured voltage 1
lt c2992 13 rev a for more information www.analog.com calculated lsb (see design example section) for current and power of both supplies have to match. otherwise, external p can be used to first compute physical amount of current and power for each supply and then perform the summing. the LTC2992 measures the current sense amplifier ?s input offset to calibrate subsequent iadc measurements. during offset measurement, iadc cannot capture load current information. by default, such calibration is done for every iadc conversion as shown in figure 2a. in most applications, the calibration frequency can be reduced by writing to ctrla register with its ctrla[7] bit set to 1. a one-off calibration is then performed immediately after the i 2 c write operation as shown in figure 2b. vadc by default monitors six input voltages sequentially as shown in figure 2a with an update rate of 10hz for each applications information input. therefore, input signals such as supply rail voltages with average value that varies at less than 5hz can be ac - curately monitored. otherwise, the input update rate can be increased by reducing the number of inputs monitored via ctrla[4:3]. figure 2c shows only the sense + pins being monitored in continuous scan mode with an effec- tive update rate of 30hz. the remaining inputs may be monitored by switching to snapshot mode when needed. a snapshot mode is available to make on-demand mea - surement of a single selected voltage without power data update (sense1 + , sense2 + , gpio1, gpio2, gpio3 or gpio4) or two selected voltages (either sense1 + and sense2 + , or gpio1 and gpio2). to make a snapshot mea - surement, write the 3-bit code of the desired voltage input to ctrla[2:0] and 01 to ctrla[6:5]. after completion of the conversion, the adcs will halt and the corresponding table 1. adc configuration via ctrla register bit name operation ctrla[7] offset calibration offset calibration for current measurements [1] = calibrate on demand [0] = every conversion (default) ctrla[6:5] measurement mode [11] = shutdown [10] = single cycle mode the vadc converts sense1 + , sense2 + , gpio1, gpio2, gpio3, gpio4 once and stops. the iadcs stop after one conversion. p1 = sense1 + ?sense1; p2 = sense2 + ?sense2 [01] = snapshot mode snapshot initializes conversion on all 3 adcs simultaneously. vadc converts the channel(s) per ctrla[2:0] [00] = continuous scan mode (default) the selected channels for vadc are defined by ctrla[4:3] ctrla[4:3] voltage selection for continuous scan mode ctrla[4:3] vadc p1 p2 11 gpio1, gpio2, gpio3, gpio4 gpio1 ?sense1 gpio2 ?sense2 10 gpio1, gpio2 gpio1 ?sense1 gpio2 ?sense2 01 sense1 + , sense2 + sense1 + ?sense1 sense2 + ?sense2 00 (default) sense1 + , sense2 + , gpio1, gpio2, gpio3, gpio4 sense1 + ?sense1 sense2 + ?sense2 ctrla[2:0] voltage selection for snapshot mode ctrla[2:0] vadc p1 p2 111 gpio1, gpio2 gpio1 ?sense1 gpio2 ?sense2 110 sense1 + , sense2 + sense1 + ?sense1 sense2 + ?sense2 101 gpio4 ?sense1/2 without p1/p2 updates 100 gpio3 011 gpio2 010 gpio1 001 sense2 + 000 (default) sense1 +
lt c2992 14 rev a for more information www.analog.com applications information figure 2 2992 f02 power up s1 s2 g1 g2 g3 g4 s1 s2 g1 g2 vadc t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms cal i1 and p1 cal i1 and p1 cal iadc1 cal (2a) continuous scan mode with calibration every cycle (default) s1, s2, g1, g2, g3, g4: sense1 + , sense2 + , gpio1, gpio2, gpio3, and gpio4 cal: calibration of current sense ampli?er i1, i2: ?sense1, ?sense2 p1, p2: power1, power2 i2 and p2 cal i2 and p2 cal iadc2 s1 s2 g1 g2 g3 g4 s1 s2 s2 g1 g2 s1 vadc cal i1 and p1 i1 and p1 i1 and p1 cal iadc1 cal (2b) continuous scan mode with on-demand calibration. ctrla[7:0] = 0x80 i2 and p2 i2 and p2 i2 and p2 cal write 0x80 to ctrla register write 0x80 to ctrla register iadc2 i1 and p1 i2 and p2 s1 s2 s1 s2 s1 s2 vadc cal i1 and p1 i1 and p1 iadc1 cal (2c) continuous scan mode with on-demand calibration. ctrla[7:0] = 0x88 i2 and p2 i2 and p2 write 0x88 to ctrla register iadc2 s1 s2 g1 g2 g3 g4 vadc cal i1 and p1 idle iadc1 cal i2 and p2 idle write 0x40 to ctrla register iadc2 s1 idle vadc cal i1 idle iadc1 cal (2d) snapshot mode for single voltage. ctrla[7:0] = 0x20 i2 idle write 0x20 to ctrla register iadc2 g1 g2 vadc cal i1 and p1 idle idle iadc1 cal (2e) snapshot mode for two voltages. ctrla[7:0] = 0x27 i2 and p2 idle write 0x27 to ctrla register iadc2 (2f) single cycle mode. ctrla[7:0] = 0x40 idle t 1 t 2 t 3 t 4 t 5 t 6 t 7
lt c2992 15 rev a for more information www.analog.com bits in adc status register (table 10) are set to indicate the availability of new data. an alert may be generated at the end of a snapshot conversion by setting bit al4[7:6] in the alert4 register (table 15). to make another snap - shot measurement, rewrite the ctrla register. figure 2d shows a snapshot operation of sense1 + with no updates to power data since only single voltage is selected while figure 2e shows combo snapshot operation of gpio1 and gpio2 with new power data. a single cycle mode allows all six voltages to be measured once with a single i 2 c command. to initiate such mode, write 10 to ctrla[6:5] as shown in figure 2f. sense1 + , sense2 + are updated together with current and power values at t 5 . at t 7 the conversions are done and the adcs are halted. if there is an extended period of i 2 c communication between the LTC2992 and the controller, some of the adc result may be lost. this is because during the i 2 c communica- tion, the adcs are prevented from updating the internal registers to avoid corrupting the data. this problem can be overcome by breaking the i 2 c communication into blocks of less than one conversion period (16.4ms for 12-bit mode and 1ms for 8-bit mode). flexible power supply the LTC2992 can be externally configured to derive power from a wide range of supplies. the LTC2992 includes an onboard linear regulator to power the low voltage inter - nal circuitry connected to the intv cc pin from high v dd voltages. the linear regulator operates with v dd voltages from 3v to 100v, and a shunt regulator is available for voltages above 100v. the linear regulator produces a 5v output capable of supplying 10ma at the intv cc pin when v dd is greater than 8v. the regulator is disabled when the applications information junction temperature rises above 150c, and the output is protected against accidental shorts. bypass capacitors of 0.1f , or greater, at both the v dd and intv cc pins are recommended for optimal transient performance. note that operation with high v dd voltages can result in significant power dissipation, and care is required to ensure that the maximum operating junction temperature stays below 125c. for improved thermal resistance, use the dfn package and solder the exposed pad to a large copper region on the pcb. figure 4a shows the LTC2992 being used to monitor input supplies that range from 4v to 100v. no separate supply is needed since v dd can be connected to either of the input supplies. to prevent loss of operation from either supply ?s failure, v dd is connected to v in1 and v in2 via diodes. if the LTC2992 is used to monitor input supplies of 0v to 100v , it can derive power from a wide range separate sup - ply connected to the v dd pin as shown in figure 4b. the (4b) derives power from a separate wide range supply (4a) derives power from the supplies being monitored figure 3. power1 generator blocks v dd gnd LTC2992 v in1 0v to 100v 3v to 100v v in2 0v to 100v v out1 v out2 intv cc 2992 f04b sense2 + sense2 ? sense1 + sense1 ? r sense1 0.01 r sense2 0.005 c2 v dd gnd bav23clt1g LTC2992 v in1 4v to 100v v in2 4v to 100v v out1 v out2 intv cc 2992 f04a sense2 + sense2 ? sense1 + sense1 ? r sense1 0.01 r sense2 0.005 c2 voltage latch accumulator latch power1 imod1 vadc data 2992 f03 +
lt c2992 16 rev a for more information www.analog.com applications information (5a) derives power through a low side shunt regulator in a high side current sense topology (5c) recommended layout for figure 5b?s sense pins connection (5b) derives power from the supply monitored in a low side current sense topology (4c) derives power from a separate low voltage supply sense +/? pins can be biased independently of the part?s supply voltage. alternatively, if a low voltage supply is present it can be connected to the intv cc pin, as shown in figure 4c, to minimize on-chip power dissipation. when intv cc is powered from a separate supply, connect v dd to intv cc . v dd gnd LTC2992 v in1 0v to 100v 2.7v to 5.8v v in2 0v to 100v v out1 v out2 intv cc 2992 f04c sense2 + sense2 ? sense1 + sense1 ? r sense1 0.01 r sense2 0.005 v dd gnd LTC2992 v in1 0v to 100v > 100v v in2 0v to 100v v out1 v out2 intv cc r shunt 2992 f05a sense2 + sense2 ? sense1 + sense1 ? r sense1 0.01 r sense2 0.005 c2 (v out ) close to the sense + terminal of the sense resistors with a wide track to prevent excessive potential difference between the sense + pins when load current is supplied entirely by v in1 or v in2 . supply undervoltage lockout during power-up, the internal i 2 c logic and the adcs are enabled when either v dd or intv cc rises above its under-voltage lockout threshold ( 2.7v for v dd and 2.5v for intv cc typically). during power-down, the adcs are disabled when v dd and intv cc fall below their respective r sense2 v out v in2 v in1 r sense1 mbr10100 mbr10100 2992 f05c 17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 bottom layer top layer gpio2 gnd c2 intv cc LTC2992 v dd v out 5a gpio1 r11 20k 2992 f05b sense2 ? sense2 + sense1 ? sense1 + r sense2 0.01 r sense1 0.01 v in2 ?5v to ?100v rtn1 rtn rtn2 v in1 ?5v to ?100v mbr10100 mbr10100 r9 1m r10 20k r8 1m mbr10100 mbr10100 figure 5a shows a high side rail-to-rail power monitor which derives power from a separate supply greater than 100v. the voltage at intv cc is clamped at 6.3v above ground in a low side shunt regulator configuration to power the part. in dual feed, low side power monitor applications, the device ground and the current sense inputs are connected to the diode-ored output of the input supplies? negative terminal as shown in figure 5b . note that the sense ? pins operate at a voltage more negative than the device ground. it is highly recommended that the sense + pins be operating at as close to device ground potential as possible so that at full-scale the sense ? pins are limited to 80mv below device ground for accurate measurements. a recom - mended layout for figure 5b?s sense pins connection is shown in figure 5c. layout the common connection
lt c2992 17 rev a for more information www.analog.com applications information undervoltage lockout thresholds. if v dd or intv cc remains above their typical 2.1v i 2 c reset threshold, the internal i 2 c logic retains the state before power-down. if v dd or intv cc is then increased as in a normal power-up, the adcs will run according to ctrla register ? s setting at that point in time. the internal i 2 c logic is reset when v dd and intv cc fall below their respective i 2 c reset thresholds. shutdown mode the LTC2992 includes a low quiescent current shutdown mode, controlled by bits ctrla[6:5] in the ctrla register (table 1). setting ctrla [6:5 ]= 11 puts the part in shutdown mode, powering down the adc, internal reference and on - board linear regulator. the internal i 2 c bus remains active, and although the adr1 and adr0 pins are disabled, the device will retain the most recently programmed i 2 c bus address. all onboard registers retain their contents and can be accessed through the i 2 c interface. to re-enable adc conversions, reset bit ctrla[6:5] in the ctrla register. the analog circuitry will power up and all registers will retain their contents. the onboard linear regulator is disabled in shutdown mode to conserve power. if the onboard linear regulator is used to power external i 2 c bus related circuitry such as opto- couplers or pull-ups, i 2 c communication will be lost when the part is shut down. the LTC2992 would then have to be reset by cycling its power to come out of shutdown. if low i q mode is not required, ensure 11 cannot be written to ctrla[6:5] in the ctrla register during software de - velopment. it is recommended that external regulators be used in such applications if powering down the LTC2992 is desirable. as an added layer of protection against this scenario, bit ctrlb[4] in the ctrlb register can be set during system configuration to enable the LTC2992 to automatically exit shutdown mode when the i 2 c lines are low for more than 33ms (which can be a result of accidental shutdown of the LTC2992?s linear regulator powering the i 2 c). the user can elect to be alerted of this event by setting bit al4[4] in the alert4 register (table 15). quiescent current drops below 50a in shutdown mode with the internal regulator disabled. configuring the gpio pins the LTC2992 has four gpio pins configurable through the gpio io control register (table 18) to be used as general purpose input/output pins. by configuring the ctrla register, the voltage at the four gpio pins can be measured by the vadc. gpio1 through gpio4 have comparators monitoring the voltage on these pins with a threshold of 1.23v typically, the results of which may be read from bits gs[3:0] in the gpio status register, as shown in table 17. an alert may be generated, when gpio1, gpio2 or gpio3 cross the comparator threshold voltage (1.23v typical), by setting bits al4[3:1] , respectively, in the alert4 register. gpio1, gpio2, gpio3 and gpio4 can be pulled low as general purpose outputs, which are otherwise high im - pedance. gpio3 can also be used as a data ready output ( dataready) to indicate new data from any of the three adcs by configuring gio[5:4] in the gpio io control register. the output can be in the form of a low pulse with duration of 16s or 128s or a latched low state. the adc status register (table 10) indicates which of the moni - tored voltages has been recently updated. this register is cleared-on-read, which will also release the gpio3 from its latched low state. gpio4 is by default an smbus alert ( alert) output that pulls low when an alert event is present. to pull gpio4 ( alert) low in the absence of an alert event, set gc[7] of the gpio4 control register (table 19). clearing this bit will release the gpio4 ( alert). gc[7] is set whenever an alert event occurs. setting gc[6] will similarly pull gpio4 low. i 2 c reset to avoid the need of power-cycling the part for a reset, LTC2992 features a software reset which is enabled by setting ctrlb[0] of ctrlb register (table 6). this bit is self-cleared. all internal registers except the present value data registers are reset to their default states. the adcs will sample continuously after reset without any reconfiguration since this is the default behavior.
lt c2992 18 rev a for more information www.analog.com applications information storing minimum and maximum values the LTC2992 compares each measurement including the calculated power with the stored values in the respective min and max registers for each parameter (table 4). if the new conversion is beyond the stored minimum or maximum values, the min or max registers are updated with the new values. the min and max registers are refreshed only when adcs update the internal registers. writing via i 2 c to the adc registers does not affect the min and max registers. to initiate a new peak hold cycle for all measurements, set ctrlb[3] of ctrlb register (table 6). this bit is self-cleared. for new peak hold cycle of selective measurement, write all 1 ?s to its min regis - ter and all 0?s to its max register via the i 2 c bus. these registers will be updated when the next respective adc conversion is done. the LTC2992 also includes min and max threshold reg - isters (table 4) for the measured parameters including the calculated power. at power-up or reset by i 2 c command, the max threshold registers are set to all 1?s, and min threshold registers are set to all 0?s, effectively disabling them. the min and max threshold registers can be repro - grammed to any desired value via the i 2 c bus. fault alert and resetting faults as soon as a measured quantity falls below the minimum threshold or exceeds the maximum threshold, the LTC2992 sets the corresponding flag in the fault1 (table 8), fault2 (table 12) and fault3 registers (table 14). other events such as gpio state change have their present status in the gpio status (table 17) register and any fault is latched in the fault4 (table 16) register. the gpio4 pin is pulled low if the appropriate bit in the alert1 (table 7), alert2 (table 11), alert3 (table 13) and alert4 (table 15) registers is set when the fault occurs. more details on the alert behavior can be found in the alert response protocol section. an active fault indication can be reset by writing zeros to the corresponding fault register bits or setting bit ctrlb[5] in the ctrlb register. if bit ctrlb[5] is set, reading the fault register will cause the corresponding register to reset. all fault register bits are also cleared if the v dd and intv cc fall below their respective i 2 c logic reset threshold. adc resolution and conversion rate the resolution of the adcs can be configured to 8-bit by setting bit nadc[7] of nadc register (table 9) through an i 2 c write command to speed up adc conversions. table 2. adc resolution and conversion rate resolution 12-bit 8-bit nadc[7] 0 1 conversion time sense + , gpio 16.4ms 1.02ms ?sense* 65.6ms 4.1ms lsb step size sense + 25mv 400mv gpio 0.5mv 8mv ?sense 12.5v 200v *snapshot mode if the resolution is changed while an adc conversion is in progress, that conversion will be aborted. in continu - ous scan mode, a new conversion of the same quantity will be started with the new resolution and continues in the original sequence. otherwise, a new snapshot of one, two or multiple quantities (single cycle) will take place. resetting the peak hold registers by setting ctrlb[3] in the ctrlb register via i 2 c bus prior to changing the adc resolution is recommended to ensure integrity of the peak hold values. the data format in 8-bit mode for voltage/current is left justified by four bits and power is left justified by eight bits with respect to the 12-bit?s format as shown in figure 6. power register value mode bit 23:20 19:16 15:12 11:8 7:4 3:0 12-bit data data data data data data 8-bit data data data data 0x0 0x0 voltage/current register value mode bit 15:12 11:8 7:4 3:0 12-bit data data data 0x0 8-bit data data 0x0 0x0 figure 6. data format in 12-bit and 8-bit mode
lt c2992 19 rev a for more information www.analog.com figure 7. configuring gpio3 as dataready adc status and data ready signal adc status register (table 10) indicates availability of new measurement results in the internal registers and is reset after it is read via i 2 c bus. details on configuring gpio3 as dataready can be found in configuring the gpio pins section. to illustrate the behavior of dataready as new data becomes available, an example in which the adcs are continuously converting is shown in figure 7. gpio3 is initially configured to output a 16s low pulse with new data as is seen at t 4 and t 5 . as s1 and s2 data are updated together with i1 and i2 at t 5 , no gpio3 pulse is seen at t 2 and t 3 . gpio3 is then reconfigured to latch low with new data ? this happens at t 6 . gpio3 is released from its latched state when an i 2 c read command to adc status register is done. crosstalk mitigation the gpio pins are general purpose pins that can be used to monitor digital or analog signals. even with an averaging architecture of the ? adcs, crosstalk may still be prob - lematic if an application requires monitoring of precision analog signals and noisy digital signals with the gpio pins. to preserve measurement accuracy of the analog signals, a few measures can be taken: 1. physically separate the clean and noisy signals. for ex - ample, the clean signal may be monitored with gpio1/3 while the noisy signal is monitored with gpio2/4 on the other side of the part. 2. if adjacent gpio pins have to be used, then decouple the analog signal to device ground near the gpio pin with an external capacitor. typically, a capacitance of 0.1f should suffice. 3. shield the sensitive signal with ground. 4. in a multi-layer pcb, the sensitive signal should be routed mostly sandwiched between two ground layers and exit next to the part for connection to the pin. a layout example is given in layout considerations section for two-layered board design. i 2 c interface the LTC2992 includes an i 2 c/smbus-compatible interface to provide access to the onboard registers. figure 8 shows a general data transfer format using the i 2 c bus. the LTC2992 is a read/write slave device and supports the smbus read byte, write byte, read word and write word protocols. the LTC2992 also supports extended read and write commands that allow reading or writing more than two bytes of data. when using the read/write word or extended read and write commands, the bus master issues an initial register address and the internal register address pointer automatically increments by 1 after each byte of data is read or written. after the register address reaches 0x 97, it will roll over to 0x00 and continue incre - menting. a stop condition resets the register address pointer to 0x 00. the data formats for the above commands are shown in figure 8 through figure 14. note that only applications information 2992 f07 power up t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 16s pulse s2 s1 g2 g1 g4 g3 s2 s1 vadc cal i1 and p1 cal i1 and p1 iadc1 cal i2 and p2 cal i2 and p2 iadc2 gpio3 i 2 c buses write reg: 0x96 data: 0x12 read reg: 0x32 data: 0x00 read reg: 0x32 data: 0x00 write reg: 0x96 data: 0x32 read reg: 0x32 data: 0xff idle idle idle idle idle
lt c2992 20 rev a for more information www.analog.com applications information the read byte command is available to the 0xe7 and 0xe8 (mfr_special_id) registers (table 4). i 2 c device addressing nine distinct i 2 c bus addresses are configurable using the three-state pins adr0 and adr1 , as shown in table 3. adr0 and adr1 should be tied to intv cc , to gnd, or left floating (nc) to configure the lower four address bits. during low power shutdown, the address select state is latched into memory powered from standby supply. address bits a6, a5 and a4 are permanently set to 110 and the least significant bit is the r/w bit. in addition, all LTC2992 devices will respond to a common mass write address (1100110)b; this allows the bus master to write to several LTC2992 s simultaneously, regardless of their individual address settings. the LTC2992 will also respond to the standard smbus ara address (0001100)b if the gpio4 ( alert) pin is asserted. see the alert response protocol section for more details. the LTC2992 will not respond to the ara address if no alerts are pending. start and stop conditions when the i 2 c bus is idle, both scl and sda are in the high state. a bus master signals the beginning of a transmis - sion with a start condition by transitioning sda from high to low while scl stays high. when the master has finished communicating with the slave, it issues a stop figure 8. general data transfer over i 2 c figure 9. serial bus sda write byte protocol figure 10. serial bus sda write word protocol figure 11. serial bus sda write page protocol figure 12. serial bus sda read byte protocol figure 14. serial bus sda read page protocol figure 13. serial bus sda read word protocol sda scl s p a6 - a0 b7 - b0 b7 - b0 1 - 7 1 - 7 1 - 7 8 8 8 9 9 9 start condition stop condition address ack data data ack ack r/w 2992 f08 s address 1 1 0 a3:a0 from master to slave from slave to master a: acknowledge (low) a: not acknowledge (high) r: read bit (high) command d ata b7:b0 0 w 0 0 0b7:b0 a a a p 2992 f09 w: write bit (low) s: start condition p: stop condition s address 1 1 0 a3:a0 command d ata d ata b7:b0 0 w 0 0 0 0 2992 f10 b7:b0 b7:b0 a a a a p s address 1 1 0 a3:a0 command 0 b7:b0 0 w 0 0 2992 f11 a a a p b7:b0 d ata 0 a b7:b0 d ata 0 a ... ... b7:b0 d ata s address 1 1 0 a3:a0 1 1 0 a3:a0 1 0 command s address r a b7:b0 1 d ata b7:b0 0 w 0 0 2992 f12 a a a p s address 1 1 0 a3:a0 1 1 0 a3:a0 1 0 command s address r a b7:b0 1 d ata b7:b0 0 w 0 0 2992 f13 a 0 a b7:b0 d ata a a p s address 1 1 0 a3:a0 1 1 0 a3:a0 1 0 command s address r a b7:b0 1 d ata b7:b0 0 w 0 0 2992 f14 a 0 a b7:b0 d ata a a p ... ... b7:b0 d ata
lt c2992 21 rev a for more information www.analog.com applications information condition by transitioning sda from low to high while scl stays high. the bus is then free for another transmission. stuck-bus reset the LTC2992 i 2 c interface features a stuck-bus reset timer to prevent it from holding the bus lines low indefinitely if the scl signal is interrupted during a transfer. the timer starts when either scl or sdai is low, and resets when both scl and sdai are pulled high. if either scl or sdai are low for over 33ms, the stuck-bus timer will expire, and the internal i 2 c interface and the sdao pin pull-down logic will be reset to release the bus. normal communication will resume at the next start command. acknowledge the acknowledge signal is used for handshaking between the master and the slave to indicate that the last byte of data was received. the master always releases the sda line during the acknowledge clock pulse. the LTC2992 will pull the sda line low on the 9th clock cycle to acknowledge receipt of the data. if the slave fails to acknowledge by leaving sda high, then the master can abort the transmis - sion by generating a stop condition. when the master is receiving data from the slave, the master must acknowledge the slave by pulling down the sda line during the 9th clock pulse to indicate receipt of a data byte. after the last byte has been received by the master, it will leave the sda line high (not acknowledge) and issue a stop condition to terminate the transmission. write protocol the master begins a write operation with a start condi - tion followed by the 7-bit slave address and the r/w bit set to zero. after the addressed LTC2992 acknowledges the address byte, the master then sends a command byte that indicates which internal register the master wishes to write. the LTC2992 acknowledges this and then latches the command byte into its internal register address pointer. the master then delivers the data byte and the LTC2992 acknowledges once more and writes the data into the in - ternal register pointed to by the register address pointer. if the master continues sending additional data bytes with a write word or extended write command, the additional data bytes will be acknowledged by the LTC2992, the register address pointer will automatically increment by one, and data will be written as previously stated. the write opera - tion terminates and the register address pointer resets to 0x00 when the master sends a stop condition. read protocol the master begins a read operation with a start condi - tion followed by the 7-bit slave address and the r/w bit set to zero. after the addressed LTC2992 acknowledges the address byte, the master then sends a command byte that indicates which internal register the master wishes to read. the LTC2992 acknowledges this and then latches the command byte into its internal register address pointer. the master then sends a repeated start condition fol - lowed by the same 7-bit address with the r/w bit now set to 1. the LTC2992 acknowledges and sends the contents of the requested register. the transmission terminates when the master sends a stop condition. if the master acknowledges the transmitted data byte, as in a read word command, the LTC2992 will send the contents of the next register. if the master keeps acknowledging, the LTC2992 will keep incrementing the register address pointer and sending out data bytes. the read operation terminates and the register address pointer resets to 0x00 when the master sends a stop condition. alert response protocol when any of the fault bits in the fault registers (fault1, fault2, fault3 and fault4) are set, a bus alert is gener - ated if the appropriate bit in the alert1, alert2, alert3 or alert4 registers has been set. this allows the bus master to select which faults will generate alerts. at power- up, all alert registers are cleared (no alerts enabled) and the gpio4 ( alert) pin is high. if an alert is enabled, the corresponding fault causes the gpio4 ( alert) pin to pull low. the bus master responds to the alert in accordance with the smbus alert response protocol by broadcasting the alert response address (0001100)b, and the LTC2992 replies with its own address and releases its gpio4 ( alert) pin, as shown in figure 15. the gpio4 ( alert) line is also released if ctrlb[7] is set and the LTC2992 is addressed (see table 6) by any message. the gpio4 ( alert ) signal
lt c2992 22 rev a for more information www.analog.com is not pulled low again until the fault registers indicate a different fault has occurred or the original fault is cleared and it occurs again. note that this means repeated or continuing faults will not generate additional alerts until the associated fault register bits have been cleared. figure 15. serial bus sda alert response protocol open-drain opto-isolators can use the LTC2992 with the sdai and sdao pins separated, as shown in figure 16. connect sdai to the output of the incoming opto-isolator with a pull-up resistor to intv cc or a local 5v supply; con - nect sdao to the cathode of the outgoing opto-isolator with a current-limiting resistor in series with the anode. the input and output must be connected together on the isolated side of the bus to allow the LTC2992 to participate in i 2 c arbitration. note that maximum i 2 c bus speed will generally be limited by the speed of the opto-couplers used in this application. figure 17 shows an alternate connection for use with low speed opto-couplers and the LTC2992 -1. this circuit uses a limited-current pull-up on the internally clamped sdai pin and clamps the sdao pin with the input diode of the outgoing opto-isolator, removing the need to use intv cc for biasing in the absence of a separate low voltage sup - ply. for proper clamping: v in(max) ? v sda,scl(min) i sda,scl(max) r4 v in(min) ? v sda,scl(max) i sda,scl(min) v in(max) ? 5.9v 5ma r4 v in(min) ? 6.9v 0.5ma (1) as an example, a supply that operates from 36v to 72v would require the value of r4 to be between 13k and 58k . the LTC2992 -1 must be used in this application to ensure that sdao signal polarity is correct. r4 may applications information scl 5v sdai sdao gnd LTC2992 scl 3.3v v dd sda gnd p 1/2 mocd207m mocd207m 2992 f16 r4 4.7k r5 4.7k r7 0.47k r8 0.47k r10 2k r6 0.82k figure 16. opto-isolation of a 10khz i 2 c interface between LTC2992 and microcontroller figure 17. opto-isolation of a 1.5khz i 2 c interface between LTC2992-1 and microcontroller (scl omitted for clarity) v in 48v sdai sdao gnd LTC2992-1 3.3v v dd sda gnd p 1/2 mocd207m 1/2 mocd207m 2992 f17 r4 20k r6 0.51k r7 2k r5 5.1k s alert response address r a 1 0001100 1 2992 f15 0 a p a7:a0 device address if two or more LTC2992s on the same bus are generat - ing alerts when the ara is broadcast, the bus master will repeat the alert response protocol until the gpio4 ( alert) line is released. standard i 2 c arbitration causes the device with the highest priority (lowest address) to reply first and the device with the lowest priority (highest address) to reply last. opto-isolating the i 2 c bus opto-isolating a standard i 2 c device is complicated by the bidirectional sda pin. the LTC2992/LTC2992 -1 minimize this problem by splitting the standard i 2 c sda line into sdai (input) and sdao (output, LTC2992) or sdao (inverted output, LTC2992 -1). the scl is an input-only pin and does not require special circuitry to isolate. for conventional nonisolated i 2 c applications, use the LTC2992 and tie the sdai and sdao pins together to form a standard i 2 c sda pin. low speed isolated interfaces that use standard
lt c2992 23 rev a for more information www.analog.com be split into two or more series connected units to meet thermal requirements. the LTC2992 can also be used with high speed optocou - plers with push-pull outputs and inverted logic as shown in figure 18. the incoming opto-isolator draws power from intv cc , and the data output is connected directly to the sdai pin with no pull-up required. ensure current drawn does not exceed the 10ma maximum capability of the intv cc pin. the sdao pin is connected to the cathode of the outgoing opto-coupler with a current limiting resistor connected back to intv cc . an additional discrete diode is required at the output of the outgoing opto-coupler to provide the open-drain pull-down that the i 2 c requires. finally, the input of the incoming opto-isolator is connected back to the output as in the low speed case. layout considerations a kelvin connection between the sense resistor r sns and the LTC2992 is recommended to achieve accurate current sensing (figure 19). the recommended minimum trace width for 1oz copper foil is 0.02? per amp to ensure the trace stays at a reasonable temperature. using 0.03 ? per amp or wider is preferred. note that 1oz copper exhibits a sheet resistance of about 530 per square. in very high current applications where the sense resistor can dissipate significant power, the pcb layout should include good thermal management techniques such as extra vias and wide metal area. 2oz or thicker copper should be considered for such applications. the trace from sense resistors to sense + pins should be as short as possible to minimize ir drop due to pin current. applications information figure 19. recommended pcb layout figure 18. opto-isolation of a i 2 c interface with low power, high speed opto-couplers (scl omitted for clarity) v in 48v sdai gnd intv cc v dd v cc 1/2 acpl-064l* bat54 iso_sda v cc *:cmos output sdao gnd LTC2992 3.3v v dd sda gnd p 2992 f18 gnd r5 2k c2 1f r6 2k r7 2k c1 1f 1/2 acpl-064l* v in2 v in1 to load2 via gnd to load1 r sns1 r sns2 2992 f19 bottom layer top layer 17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8
lt c2992 24 rev a for more information www.analog.com applications information design example as a design example, consider a ?36v to ?72v advanced tca system with i 2 c current, voltage and power monitors (see figure 20). the load current is either supplied by v in1 or v in2 or both depending on their voltages. choose similar values for r sense1 and r sense2 in accordance to the following equation: r sense1,2 < v fs( ? sense1,2) i load(max) r sense1,2 < 51.2mv 5a = 10.24m r sense1 and r sense2 are chosen to be 10m. current of v in1 or v in2 = 12.5v r sense = 1.25ma / lsb total current = 2.5ma/lsb we also have to consider the power dissipated in the sense resistors which can be calculated with the follow - ing equation: p = (i load ) 2 ? r sense p = (5a) 2 ? 10m = 0.25w use at least 0.5w rated sense resistors to ensure thermal compliance. next, select the resistive dividers that measure the supply voltages v in1 and v in2. note that the voltage drop across the n-channel mosfet and sense resistor is not included in the derivation for the following equations. r12 r10 + r12 < v fs(gpio2) v in2 , r13 r11 + r13 < v fs(gpio1) v in1 r12 r10 + r12 < 2.048v 72v = 0.028 r13 r11 + r13 < 2.048v 72v = 0.028 choose r10,11 = 1m , and r12,13 = 20k to allow a input voltage measurement range from 0v to 104.4v. voltage of v in1 = r11 + r13 r13 ? v gpio1 = 25.5mv lsb voltage of v in2 = r10 + r12 r12 ? v gpio2 = 25.5mv lsb an error term can be added to the voltage results above to account for the voltage drop across the n-channel mosfet and sense resistor: v error = ?v ds of fds3672 + ?sense the maximum error occurs when the load current is at its maximum of 5a. using the above equation, this works out to be 160mv with 110mv contribution (see below for calculation) from the fd s3672 . without compensation, this would cause measurement error of 0.45% for v in = 36v. ltc4354 and ltc4355 low side and high side ideal diode- or controllers drive n-channel mosfets to minimize the diode power consumption. the 100v, n-channel mosfet fds3672 in the so-8 package with r ds(on) = 22m (max) is chosen as switches. the maximum voltage drop across it is: ?v ds = 5a 22m = 110mv since external resistive dividers are used for supply volt - age measurement, ctrla register 0x 00 is set to 0x 10 to continuously monitor gpio1 and gpio2. power1 = v in1 ? current of v in1 power1 = 25.5mv ? 1.25ma/lsb = 31.875w/lsb power2 = 31.875w/lsb total power = 63.75w/lsb
lt c2992 25 rev a for more information www.analog.com applications information figure 20. design example: advanced tca system with i 2 c current, voltage and power monitors gpio2 gpio4 gnd sdao adr0 adr1 dataready sdai scl c4 0.1f LTC2992 v dd intv cc gpio1 gpio3 c3 1f db da ga gb v ss v ss ltc4354 v cc gate1 in1 in2 q3 fds3672 q4 fds3672 gate2 out ltc4355 gnd mon2 mon1 sense2 ? sense2 + sense1 ? sense1 + r sense2 0.01 r sense1 0.01 gnd gnd v cc 3.3v acpl-064l acpl-064l 2992 f20 v out 5a alert v cc r1 1k r2 1k r5 0.51k c1 0.1f r4 51k r6 0.51k r7 1k r8 1k v dd 3.3v int sda scl gnd p r13 2k r14 2k q5 fds3672 q6 fds3672 v in2 ?36v to ?72v v in1 ?36v to ?72v r9 12k 0.5w r3 91 z1 smbt70a c2 22nf q1 pzta42 rtn(out) q2 mmbt5401 r12 20k r13 20k r10 1m rtn1 rtn2 r11 1m
lt c2992 26 rev a for more information www.analog.com applications information table 3. device addressing address description hex device address* binary device addressing address pins 7-bit 8-bit a6 a5 a4 a3 a2 a1 a0 r/ w adr1 adr0 mass write 66 cc 1 1 0 0 1 1 0 0 x x alert response 0c 19 0 0 0 1 1 0 0 1 x x 0 67 ce 1 1 0 0 1 1 1 0 h l 1 68 d0 1 1 0 1 0 0 0 0 nc h 2 69 d2 1 1 0 1 0 0 1 0 h h 3 6a d4 1 1 0 1 0 1 0 0 nc nc 4 6b d6 1 1 0 1 0 1 1 0 nc l 5 6c d8 1 1 0 1 1 0 0 0 l h 6 6d da 1 1 0 1 1 0 1 0 h nc 7 6e dc 1 1 0 1 1 1 0 0 l nc 8 6f de 1 1 0 1 1 1 1 0 l l h = tie to intv cc , nc = no connect = open, l = tie to gnd, x = don?t care *8-bit hexadecimal address with lsb r/w bit = 0 7-bit hexadecimal address with msb a7 = 0 table 4. register addresses and contents register name register address description read/ write number of bytes* default ctrla 0x00 operation control register a r/w 1 0x00 ctrlb 0x01 operation control register b r/w 1 0x00 alert1 0x02 selects which channel 1 faults generate alerts r/w 1 0x00 fault1 0x03 channel 1 fault log r/w 1 0x00 nadc 0x04 adc resolution r/w 1 0x00 p1 0x05-0x07 power1 data r/w 3 na max p1 0x08-0x0a maximum power1 data r/w 3 na min p1 0x0b-0x0d minimum power1 data r/w 3 na max p1 threshold 0x0e-0x10 maximum power1 threshold to generate alert r/w 3 0xffffff min p1 threshold 0x11-0x13 minimum power1 threshold to generate alert r/w 3 0x000000 i1 0x14-0x15 ?sense1 data r/w 2 na max i1 0x16-0x17 maximum ?sense1 data r/w 2 na min i1 0x18-0x19 minimum ?sense1 data r/w 2 na max i1 threshold 0x1a-0x1b maximum ?sense1 threshold to generate alert r/w 2 0xfff0 min i1 threshold 0x1c-0x1d minimum ?sense1 threshold to generate alert r/w 2 0x0000 s1 0x1e-0x1f sense1 + data r/w 2 na max s1 0x20-0x21 maximum sense1 + data r/w 2 na min s1 0x22-0x23 minimum sense1 + data r/w 2 na
lt c2992 27 rev a for more information www.analog.com applications information table 4. register addresses and contents register name register address description read/ write number of bytes default max s1 threshold 0x24-0x25 maximum sense1 + threshold to generate alert r/w 2 0xfff0 min s1 threshold 0x26-0x27 minimum sense1 + threshold to generate alert r/w 2 0x0000 g1 0x28-0x29 gpio1 data r/w 2 na max g1 0x2a-0x2b maximum gpio1 data r/w 2 na min g1 0x2c-0x2d minimum gpio1 data r/w 2 na max g1 threshold 0x2e-0x2f maximum gpio1 threshold to generate alert r/w 2 0xfff0 min g1 threshold 0x30-0x31 minimum gpio1 threshold to generate alert r/w 2 0x0000 adc status 0x32 adc status information r 1 na reserved 0x33 manufacturer reserved r 1 0x00 alert2 0x34 selects which channel 2 faults generate alerts r/w 1 0x00 fault2 0x35 channel 2 fault log r/w 1 0x00 reserved 0x36 manufacturer reserved r 1 0x00 p2 0x37-0x39 power2 data r/w 3 na max p2 0x3a-0x3c maximum power2 data r/w 3 na min p2 0x3d-0x3f minimum power2 data r/w 3 na max p2 threshold 0x40-0x42 maximum power2 threshold to generate alert r/w 3 0xffffff min p2 threshold 0x43-0x45 minimum power2 threshold to generate alert r/w 3 0x000000 i2 0x46-0x47 ?sense2 data r/w 2 na max i2 0x48-0x49 maximum ?sense2 data r/w 2 na min i2 0x4a-0x4b minimum ?sense2 data r/w 2 na max i2 threshold 0x4c-0x4d maximum ?sense2 threshold to generate alert r/w 2 0xfff0 min i2 threshold 0x4e-0x4f minimum ?sense2 threshold to generate alert r/w 2 0x0000 s2 0x50-0x51 sense2 + data r/w 2 na max s2 0x52-0x53 maximum sense2 + data r/w 2 na min s2 0x54-0x55 minimum sense2 + data r/w 2 na max s2 threshold 0x56-0x57 maximum sense2 + threshold to generate alert r/w 2 0xfff0 min s2 threshold 0x58-0x59 minimum sense2 + threshold to generate alert r/w 2 0x0000 g2 0x5a-0x5b gpio2 data r/w 2 na max g2 0x5c-0x5d maximum gpio2 data r/w 2 na min g2 0x5e-0x5f minimum gpio2 data r/w 2 na max g2 threshold 0x60-0x61 maximum gpio2 threshold to generate alert r/w 2 0xfff0 (continued)
lt c2992 28 rev a for more information www.analog.com applications information table 4. register addresses and contents register name register address description read/ write number of bytes default min g2 threshold 0x62-0x63 minimum gpio2 threshold to generate alert r/w 2 0x0000 g3 0x64-0x65 gpio3 data r/w 2 na max g3 0x66-0x67 maximum gpio3 data r/w 2 na min g3 0x68-0x69 minimum gpio3 data r/w 2 na max g3 threshold 0x6a-0x6b maximum gpio3 threshold to generate alert r/w 2 0xfff0 min g3 threshold 0x6c-0x6d minimum gpio3 threshold to generate alert r/w 2 0x0000 g4 0x6e-0x6f gpio4 data r/w 2 na max g4 0x70-0x71 maximum gpio4 data r/w 2 na min g4 0x72-0x73 minimum gpio4 data r/w 2 na max g4 threshold 0x74-0x75 maximum gpio4 threshold to generate alert r/w 2 0xfff0 min g4 threshold 0x76-0x77 minimum gpio4 threshold to generate alert r/w 2 0x0000 isum 0x78-0x79 (?sense1 + ?sense2) data r/w 2 na max isum 0x7a-0x7b maximum (?sense1 + ?sense2) data r/w 2 na min isum 0x7c-0x7d minimum (?sense1 + ?sense2) data r/w 2 na max isum threshold 0x7e-0x7f maximum (?sense1 + ?sense2) threshold to generate alert r/w 2 0xfff0 min isum threshold 0x80-0x81 minimum (?sense1 + ?sense2) threshold to generate alert r/w 2 0x0000 psum 0x82-0x84 (power1 + power2) data r/w 3 na max psum 0x85-0x87 maximum (power1 + power2) data r/w 3 na min psum 0x88-0x8a minimum (power1 + power2) data r/w 3 na max psum threshold 0x8b-0x8d maximum (power1 + power2) threshold to generate alert r/w 3 0xffffff min psum threshold 0x8e-0x90 minimum (power1 + power2) threshold to generate alert r/w 3 0x000000 alert3 0x91 selects which gpio or total current/power faults generate alerts r/w 1 0x00 fault3 0x92 gpio and total current/power fault log r/w 1 0x00 alert4 0x93 selects which additional faults generate alerts r/w 1 0x00 fault4 0x94 additional fault log r/w 1 0x00 gpio status 0x95 gpio status information r 1 na gpio io control 0x96 gpio1,2,3 input/output control command r/w 1 0x03 gpio4 control 0x97 gpio4 control command r/w 1 0x00 mfr_special_id msb 0xe7 manufacturer special id msb data r 1 0x00 mfr_special_id lsb 0xe8 manufacturer special id lsb data r 1 0x62 * for the 2-/3-byte data registers, the msb value is at the lowest address (continued)
lt c2992 29 rev a for more information www.analog.com applications information table 5. ctrla register (0x00) ? read/write bit name operation ctrla[7] offset calibration offset calibration for current measurements [1] = calibrate on demand [0] = every conversion (default) ctrla[6:5] measurement mode [11] = shutdown [10] = single cycle mode the vadc converts sense1 + , sense2 + , gpio1, gpio2, gpio3, gpio4 once and stops. the iadcs stop after one conversion. p1 = sense1 + ?sense1; p2 = sense2 + ?sense2 [01] = snapshot mode snapshot initializes conversion on all 3 adcs simultaneously. vadc converts the channel(s) per ctrla[2:0] [00] = continuous scan mode (default) the selected channels for vadc are defined by ctrla[4:3] ctrla[4:3] voltage selection for continuous scan mode ctrla[4:3] vadc p1 p2 11 gpio1, gpio2, gpio3, gpio4 gpio1 ?sense1 gpio2 ?sense2 10 gpio1, gpio2 gpio1 ?sense1 gpio2 ?sense2 01 sense1 + , sense2 + sense1 + ?sense1 sense2 + ?sense2 00 (default) sense1 + , sense2 + , gpio1, gpio2, gpio3, gpio4 sense1 + ?sense1 sense2 + ?sense2 ctrla[2:0] voltage selection for snapshot mode ctrla[2:0] vadc p1 p2 111 gpio1, gpio2 gpio1 ?sense1 gpio2 ?sense2 110 sense1 + , sense2 + sense1 + ?sense1 sense2 + ?sense2 101 gpio4 ?sense1/2 without p1/p2 updates 100 gpio3 011 gpio2 010 gpio1 001 sense2 + 000 (default) sense1 + table 6. ctrlb register (0x01) ? read/write bit name operation ctrlb[7] alert clear enable clear alert if device is addressed by the master [1] = enable [0] = disable (default) ctrlb[6] reserved always returns 0, not writable ctrlb[5] cleared on read control fault registers cleared on read [1] = cleared on read [0] = registers not affected by reading (default) ctrlb[4] stuck bus timeout auto wake up allows part to exit shutdown mode when stuck bus timer is reached [1] = enable [0] = disable (default) ctrlb[3] peak hold values reset reset of min and max registers [1] = reset all min and max registers [0] = disable reset of min and max registers (default) ctrlb[2:1] reserved always returns 00, not writable ctrlb[0] reset [1] = reset all registers [0] = disable reset (default)
lt c2992 30 rev a for more information www.analog.com applications information table 7. alert1 register (0x02) ? read/write bit name operation al1[7] maximum power1 alert enables alert when power1 > maximum power1 threshold [1] = enable alert [0] = disable alert (default) al1[6] minimum power1 alert enables alert when power1 < minimum power1 threshold [1] = enable alert [0] = disable alert (default) al1[5] maximum ?sense1 alert enables alert when ?sense1 > maximum ?sense1 threshold [1] = enable alert [0] = disable alert (default) al1[4] minimum ?sense1 alert enables alert when ?sense1 < minimum ?sense1 threshold [1] = enable alert [0] = disable alert (default) al1[3] maximum sense1 + alert enables alert when sense1 + > maximum sense1 + threshold [1] = enable alert [0] = disable alert(default) al1[2] minimum sense1 + alert enables alert when sense1 + < minimum sense1 + threshold [1] = enable alert [0] = disable alert (default) al1[1] maximum gpio1 alert enables alert when gpio1 > maximum gpio1 threshold [1] = enable alert [0] = disable alert (default) al1[0] minimum gpio1 alert enables alert when gpio1 < minimum gpio1 threshold [1] = enable alert [0] = disable alert (default) table 8. fault1 register (0x03) ? read/write bit name operation f1[7] power1 overvalue fault power1 > maximum power1 threshold [1] = power1 overvalue fault occurred [0] = no power1 overvalue fault occurred (default) f1[6] power1 undervalue fault power1 < minimum power1 threshold [1] = power1 undervalue fault occurred [0] = no power1 undervalue fault occurred (default) f1[5] ?sense1 overvalue fault ?sense1 > maximum ?sense1 threshold [1] = ?sense1 overvalue fault occurred [0] = no ?sense1 overvalue fault occurred (default) f1[4] ?sense1 undervalue fault ?sense1 < minimum ?sense1 threshold [1] = ?sense1 undervalue fault occurred [0] = no ?sense1 undervalue fault occurred (default) f1[3] sense1 + overvalue fault sense1 + > maximum sense1 + threshold [1] = sense1 + overvalue fault occurred [0] = no sense1 + overvalue fault occurred (default) f1[2] sense1 + undervalue fault sense1 + < minimum sense1 + threshold [1] = sense1 + undervalue fault occurred [0] = no sense1 + undervalue fault occurred (default) f1[1] gpio1 overvalue fault gpio1 > maximum gpio1 threshold [1] = gpio1 overvalue fault occurred [0] = no gpio1 overvalue fault occurred (default) f1[0] gpio1 undervalue fault gpio1 < minimum gpio1 threshold [1] = gpio1 undervalue fault occurred [0] = no gpio1 undervalue fault occurred (default)
lt c2992 31 rev a for more information www.analog.com applications information table 9. nadc register (0x04) ? read/write bit name operation nadc[7] adc resolution selects adc resolution for all adcs [1] = 8-bit [0] = 12-bit (default) nadc[6:0] reserved always returns 0000000, not writable table 10. adc status register (0x32) ? read only (clear-on-read) bit name operation as[7] iadcs data ready [1] = ready [0] = not ready as[6] vadc data ready [1] = ready [0] = not ready check as[5:0] for the channel information as[5] gpio4 data ready [1] = new data available [0] = new data not available as[4] gpio3 data ready [1] = new data available [0] = new data not available as[3] gpio2 data ready [1] = new data available [0] = new data not available as[2] gpio1 data ready [1] = new data available [0] = new data not available as[1] sense2 + data ready [1] = new data available [0] = new data not available as[0] sense1 + data ready [1] = new data available [0] = new data not available table 11. alert2 register (0x34) ? read/write bit name operation al2[7] maximum power2 alert enables alert when power2 > maximum power2 threshold [1] = enable alert [0] = disable alert (default) al2[6] minimum power2 alert enables alert when power2 < minimum power2 threshold [1] = enable alert [0] = disable alert (default) al2[5] maximum ?sense2 alert enables alert when ?sense2 > maximum ?sense2 threshold [1] = enable alert [0] = disable alert (default) al2[4] minimum ?sense2 alert enables alert when ?sense2 < minimum ?sense2 threshold [1] = enable alert [0] = disable alert (default) al2[3] maximum sense2 + alert enables alert when sense2 + > maximum sense2 + threshold [1] = enable alert [0] = disable alert (default) al2[2] minimum sense2 + alert enables alert when sense2 + < minimum sense2 + threshold [1] = enable alert [0] = disable alert (default) al2[1] maximum gpio2 alert enables alert when gpio2 > maximum gpio2 threshold [1] = enable alert [0] = disable alert (default) al2[0] minimum gpio2 alert enables alert when gpio2 < minimum gpio2 threshold [1] = enable alert [0] = disable alert (default)
lt c2992 32 rev a for more information www.analog.com applications information table 12. fault2 register (0x35) ? read/write bit name operation f2[7] power2 overvalue fault power2 > maximum power2 threshold [1] = power2 overvalue fault occurred [0] = no power2 overvalue fault occurred (default) f2[6] power2 undervalue fault power2 < minimum power2 threshold [1] = power2 undervalue fault occurred [0] = no power2 undervalue fault occurred (default) f2[5] ?sense2 overvalue fault ?sense2 > maximum ?sense2 threshold [1] = ?sense2 overvalue fault occurred [0] = no ?sense2 overvalue fault occurred (default) f2[4] ?sense2 undervalue fault ?sense2 < minimum ?sense2 threshold [1] = ?sense2 undervalue fault occurred [0] = no ?sense2 undervalue fault occurred (default) f2[3] sense2 + overvalue fault sense2 + > maximum sense2 + threshold [1] = sense2 + overvalue fault occurred [0] = no sense2 + overvalue fault occurred (default) f2[2] sense2 + undervalue fault sense2 + < minimum sense2 + threshold [1] = sense2 + undervalue fault occurred [0] = no sense2 + undervalue fault occurred (default) f2[1] gpio2 overvalue fault gpio2 > maximum gpio2 threshold [1] = gpio2 overvalue fault occurred [0] = no gpio2 overvalue fault occurred (default) f2[0] gpio2 undervalue fault gpio2 < minimum gpio2 threshold [1] = gpio2 undervalue fault occurred [0] = no gpio2 undervalue fault occurred (default) table 13. alert3 register (0x91) ? read/write bit name operation al3[7] maximum gpio3 alert enables alert when gpio3 > maximum gpio3 threshold [1] = enable alert [0] = disable alert (default) al3[6] minimum gpio3 alert enables alert when gpio3 < minimum gpio3 threshold [1] = enable alert [0] = disable alert (default) al3[5] maximum gpio4 alert enables alert when gpio4 > maximum gpio4 threshold [1] = enable alert [0] = disable alert (default) al3[4] minimum gpio4 alert enables alert when gpio4 < minimum gpio4 threshold [1] = enable alert [0] = disable alert (default) al3[3] maximum (?sense1 + ?sense2) alert enables alert when (?sense1 + ?sense2) > maximum (?sense1 + ?sense2) threshold [1] = enable alert [0] = disable alert (default) al3[2] minimum (?sense1 + ?sense2) alert enables alert when (?sense1 + ?sense2) < minimum (?sense1 + ?sense2) threshold [1] = enable alert [0] = disable alert (default) al3[1] maximum (power1 + power2) alert enables alert when (power1 + power2) > maximum (power1 + power2) threshold [1] = enable alert [0] = disable alert (default) al3[0] minimum (power1 + power2) alert enables alert when (power1 + power2) < minimum (power1 + power2) threshold [1] = enable alert [0] = disable alert (default)
lt c2992 33 rev a for more information www.analog.com applications information table 14. fault3 register (0x92) ? read/write bit name operation f3[7] gpio3 overvalue fault gpio3 > maximum gpio3 threshold [1] = gpio3 overvalue fault occurred [0] = no gpio3 overvalue fault occurred (default) f3[6] gpio3 undervalue fault gpio3 < minimum gpio3 threshold [1] = gpio3 undervalue fault occurred [0] = no gpio3 undervalue fault occurred (default) f3[5] gpio4 overvalue fault gpio4 > maximum gpio4 threshold [1] = gpio4 overvalue fault occurred [0] = no gpio4 overvalue fault occurred (default) f3[4] gpio4 undervalue fault gpio4 < minimum gpio4 threshold [1] = gpio4 undervalue fault occurred [0] = no gpio4 undervalue fault occurred (default) f3[3] (?sense1 + ?sense2) overvalue fault (?sense1 + ?sense2) > maximum (?sense1 + ?sense2) threshold [1] = summed current overvalue fault occurred [0] = no summed current overvalue fault occurred (default) f3[2] (?sense1 + ?sense2) undervalue fault (?sense1 + ?sense2) < minimum (?sense1 + ?sense2) threshold [1] = summed current undervalue fault occurred [0] = no summed current undervalue fault occurred (default) f3[1] (power1 + power2) overvalue fault (power1 + power2) > maximum (power1 + power2) threshold [1] = summed power overvalue fault occurred [0] = no summed power overvalue fault occurred (default) f3[0] (power1 + power2) undervalue fault (power1 + power2) < minimum (power1 + power2) threshold [1] = summed power undervalue fault occurred [0] = no summed power undervalue fault occurred (default) table 15. alert4 register (0x93) ? read/write bit name operation al4[7] vadc data ready alert alert when vadc data ready [1] = enable [0] = disable (default) al4[6] iadc data ready alert alert when iadcs data ready [1] = enable [0] = disable (default) al4[5] reserved always returns 0, not writable al4[4] stuck bus time-out wakeup alert alert if part exits shutdown mode after stuck bus timer expires with ctrlb[4] = 1 [1] = enable alert [0] = disable alert (default) al4[3] gpio1 input alert [1] = enable alert [0] = disable alert (default) al4[2] gpio2 input alert [1] = enable alert [0] = disable alert (default) al4[1] gpio3 input alert [1] = enable alert [0] = disable alert(default) al4[0] reserved always returns 0, not writable
lt c2992 34 rev a for more information www.analog.com applications information table 16. fault4 register (0x94) ? read/write bit name operation f2[7:5] reserved always returns 000, not writable f4[4] stuck bus time-out wakeup fault with ctrlb[4] = 1 [1] = part exited shutdown mode after stuck bus timer expired [0] = no stuck bus time-out wakeup fault occurred (default) f4[3] gpio1 input fault [1] = gpio1 input was at alert level [0] = gpio1 input was not at alert level (default) alert polarity is set in gio[3] (table 18) f4[2] gpio2 input fault [1] = gpio2 input was at alert level [0] = gpio2 input was not at alert level (default) alert polarity is set in gio[2] (table 18) f4[1] gpio3 input fault [1] = gpio3 input was at alert level [0] = gpio3 input was not at alert level (default) alert polarity is set in gio[1] (table 18) f4[0] reserved always returns 0, not writable table 17. gpio status register (0x95) ? read only bit name operation gs[7:4] reserved always returns 0000, not writable gs[3] gpio1 state [1] = gpio1 high [0] = gpio1 low gs[2] gpio2 state [1] = gpio2 high [0] = gpio2 low gs[1] gpio3 state [1] = gpio3 high [0] = gpio3 low gs[0] gpio4 state [1] = gpio4 high [0] = gpio4 low table 18. gpio io control register (0x96) ? read/write bit name operation gio[7] gpio1 output [1] = pulls low [0] = hi-z (default) gio[6] gpio2 output [1] = pulls low [0] = hi-z (default) gio[5:4] gpio3 configuration [11] = pulls low when any of the adcs data becomes ready, resets to high by reading adc status register 0x32 [10] = 128s low pulse when any of the adcs data becomes available [01] = 16s low pulse when any of the adcs data becomes available [00] = general purpose input/output (default) gio[3] gpio1 alert polarity configuration [1] = alert on gpio1 input high [0] = alert on gpio1 input low (default) gio[2] gpio2 alert polarity configuration [1] = alert on gpio2 input high [0] = alert on gpio2 input low (default) gio[1] gpio3 alert polarity configuration [1] = alert on gpio3 input high (default) [0] = alert on gpio3 input low gio[0] gpio3 output [1] = pulls low (default) [0] = hi-z
lt c2992 35 rev a for more information www.analog.com applications information table 19. gpio4 control register (0x97) ? read/write bit name operation gc[7] alert generated [1] = alert generated [0] = no alert generated latched to 1 when an alert is generated and can be cleared via i 2 c by writing a 0 to it or setting ctrlb[7] (table 6) to 1 gc[6] gpio4 output [1] = pulls low [0] = hi-z (default) gc[5:0] reserved always returns 000000, not writable table 20. register data format ? read/write: adc, min/max adc, min/max adc threshold, isum, min/max isum, min/max isum threshold 12-bit mode: bit(7) bit(6) bit(5) bit(4) bit(3) bit(2) bit(1) bit(0) msb register data(11) data(10) data(9) data(8) data(7) data(6) data(5) data(4) lsb register data(3) data(2) data(1) data(0) 0 0 0 0 8-bit mode: bit(7) bit(6) bit(5) bit(4) bit(3) bit(2) bit(1) bit(0) msb2 register data(15) data(14) data(13) data(12) data(11) data(10) data(9) data(8) msb1 register data(7) data(6) data(5) data(4) data(3) data(2) data(1) data(0) lsb register 0 0 0 0 0 0 0 0 table 21. register data format ? read/write: power, min/max power, min/max power threshold, psum, min/max psum, min/max psum threshold 12-bit mode: bit(7) bit(6) bit(5) bit(4) bit(3) bit(2) bit(1) bit(0) msb2 register data(23) data(22) data(21) data(20) data(19) data(18) data(17) data(16) msb1 register data(15) data(14) data(13) data(12) data(11) data(10) data(9) data(8) lsb register data(7) data(6) data(5) data(4) data(3) data(2) data(1) data(0) 8-bit mode: bit(7) bit(6) bit(5) bit(4) bit(3) bit(2) bit(1) bit(0) msb register data(7) data(6) data(5) data(4) data(3) data(2) data(1) data(0) lsb register 0 0 0 0 0 0 0 0
lt c2992 36 rev a for more information www.analog.com typical applications ?48v redundant feed with transient protection to 200v (1.5khz i 2 c interface) high side and low side current sensing on a wide range supply r sense1 0.01 r sense2 0.01 2992 ta03 adr1 gnd LTC2992 v dd intv cc adr0 sdao scl sdai c1 1f r1 40.2k 1% gpio1 gpio2 gpio4 gpio3 alert gp output i 2 c interface v in 7v to 100v sense2 ? sense2 + sense1 + sense1 ? r3 19.1k 1% vishay ntcs0402e3104*ht 100k at 25c 1% r2 10k 1% r4 20k 1% + ? load 5a t(c) = 41.51 ? ( ? 0.1233), 20c < t < 60c epee code gpio code gpio2 gpio2 gnd gpio4 sdao adr0 adr1 sdai scl LTC2992-1 v dd intv cc gpio1 gpio3 temperature sensor sense1 ? sense1 + sense2 ? sense2 + r sense1 0.01 r sense2 0.01 mbr20200* mbr20200* mocd207m mocd207m v out 5a 2992 ta02 alert r3 1k r4 0.51k r1 2k r9 0.51k r10 0.51k r11 2k r12 2k r13 10k v dd 3.3v int sda scl gnd p c1 1f v in1 ?48v v in2 ?48v r8 20k r7 20k r6 1m rtn1 rtn2 r5 1m *appropriately sized heat sink is required r shunt2 9.1k 1w r shunt1 9.1k 1w r2 2k mbr20200* mbr20200* r14 100 q1, pzta42
lt c2992 37 rev a for more information www.analog.com typical applications dual 12v high power monitor with one negative voltage monitor r sense1 0.5m r sense2 0.5m 2992 ta04 1.8v 4mv/k LTC2992 v dd intv cc sdao scl sdai c1 1f gpio1 gpio2 gpio4 gpio3 adr0 adr1 gnd alert dataready i 2 c interface sense2 + sense2 ? sense1 + sense1 ? v neg 0v to ?60v v in2 12v v out2 100a v in1 12v v out1 100a c2 470pf mmbt3904 measures board temperature d + d ? v ptat v cc v ref gnd temperature ltc2997 r1 640k 1% r2 17.8k 1% r sense1_10 5m r sp1_10 1 r sm1_10 1 r sense1_1 5m r sp1_1 1 r sm1_1 1 ? ? ? t(c) = code gpio2 /8 ? 273.15 v neg (v) = 36.955 code gpio1 gpio lsb step size ? 64.7191, ?60v < v neg < 0v r sense1 = resistor array 10 5m parallel sense resistors 10 pairs of 1 resistors
lt c2992 38 rev a for more information www.analog.com typical applications power monitor for 48v, 500w electric bike/scooter gpio1 gpio2 adr1 adr0 gnd intv cc gp output gpio4 gpio3 scl sdao sdai LTC2992 v dd 48v sense2 + sense2 ? sense1 + r sense1 0.2 r sense2 0.005 sense1 ? r3 330k r4 10k r5 10k v dd mcu gnd 3.3v 10a int alert scl headlight relay control sda pin not used in ltc2997 circuit: v ref temperature t(c) = code gpi01 /8 ? 273.15 2992 ta05 4mv/k measure board temperature dc brushless motor mmbt3904 r6 10k c1, 1f gnd ltc2997 d + d ? v cc v ptat r2 10k c2 470pf 200ma + ?
lt c2992 39 rev a for more information www.analog.com typical applications four quadrant power monitor (10khz i 2 c interface) gpio2 gpio4 adr1 adr0 gnd sdao sdai scl LTC2992-1 v dd nc nc intv cc gpio1 gpio3 v in ?95v to 100v orgnd (gnd pin of LTC2992-1) sense2 ? sense1 + sense1 ? sense2 + mocd207m mocd207m 2992 ta06 alert r6 33k r7 0.82k r8 4.7k r10 0.47k r11 0.47k r12 2k r13 2k r14 10k v dd 3.3v int sda scl gnd p r17 100k r16 100k r4 1m separate 5v supply temperature sensor r9 4.7k pin not used in ltc4371 circuit: faultb nc: no connect if code gpio1 > code gpio2 , measured v in = ?[code gpio1 gpio lsb step size 51] if code gpio1 < code gpio2 , measured v in = code gpio2 gpio lsb step size 51 v ds,q2 , v ds,q3 are drain to source voltage of q2 and q3 v rsense is voltage across r sense *max emitter-base breakdown voltage of q4, q5 should be less than 7v c1 1f orgnd q4* mmbt2222l q1 pzta42 sb ltc4371 sa ga da gb v out 5a db v ss v z v dd c3 1nf r15, 10k c2 1nf q3 bsp297 q2 bsp297 r sense 0.01 q5* mmbt2222l + ? r1 1m r3 20k r2 20k |v in | ? |v rsense |?|v ds,q2 | 51 1 gpio lsb step size |v in | ? |v ds,q3 | 51 1 gpio lsb step size code gpio1 = code gpio2 =
lt c2992 40 rev a for more information www.analog.com typical applications power efficiency meter c a 0.1f LTC2992 sdai sdao scl sense2 ? sense2 + intv cc adr1 adr0 gnd gpio1 gpio4 gpio2 gpio3 v dd sense1 + sense1 ? r pu4 100k alert ltc3895 v in run mode ilim tg boost sw bg sense + sense ? v fb ith drv cc 2992 ta07 drvset drvuv r pu3 100k r b , 140k r pu2 100k ovlo pins not used in ltc3895 circuit: clkout, pllin, phasmd, pgood, vprg mtop, mbot: bsc520n15ns3g d ext : diodes inc. smaz12-13-f l1: wurth 7443633300 c outa : suncon 35ce68lx ndrv intv cc crump_en ss extv cc c b 0.1f l1, 33h freq gnd gnd gnd gnd c sns 1nf mbot mtop 2 c ithb 100pf c itha 4.7nf r freq 30.1k r drv 80.6k r ith 10k r a 10k c ext 1f r pu1 100k c ina 100f r sense1 10m r sense2 6m v in 14v to 100v i 2 c interface + c inb 0.47f 4 c intvcc 0.1f c drvcc 4.7f c ss 0.1f c outa 150f 2 v out 12v 5a + c outb 22f
lt c2992 41 rev a for more information www.analog.com typical applications bidirectional 30v to 300v high side power monitor gpio2 nst30010mxv6 gpio4 gpio3 gnd LTC2992 gpio1 sense1 ? sense2 + sense2 ? sense1 + 2992 ta08 adr0 adr1 sdao sdai scl intv cc v dd adum1251 v dd2 sda 2 scl 2 gnd 2 v dd1 sda 1 scl 1 gnd 1 use gpio to measure input voltage see table 5 *ddz9689, diodes inc. r sense 0.01 v in r11 100 q2 mmbt6520l q1 2n3904 m3 bsp135 r12 374k r13 374k r6 10k r5 10k m1 bsp135 q3 2n3904 fan on output alert r3 5k c2 0.1f v out 5a r4 2k r7 2k r8 1k r9 1k r10 10k v dd p 3.3v c1 0.1f r1 2k z1* 5.1v r11 2k r2 5.1k sda scl int gnd fodm217c
lt c2992 42 rev a for more information www.analog.com typical applications bipolar supply power monitor (1.5khz i 2 c interface) gpio2 gnd intv cc gpio3 gpio4 adr0 adr1 sdao sdai scl LTC2992-1 v dd gpio1 sense2 ? sense2 + sense1 + sense1 ? mocd207m mocd207m 2992 ta09 alert r4 15k r5 3.3k r6 15k r8 0.2k r9 0.2k r10 2k r11 2k r12 10k v dd 3.3v int sda scl gnd p v neg ?10v to ?20v v pos 10v to 20v 5a temperature sensor *diodes ensure LTC2992-1?s operation when either supply fails open r7 15k 5a bat54* bat54* r sense2 0.01 r sense1 0.01 c1 1f r1 118k r2 10k r3 10k
lt c2992 43 rev a for more information www.analog.com package description please refer to http://www.linear.com/product/LTC2992#packaging for the most recent package drawings. 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.15 ref 1.70 0.05 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de16) dfn 0806 rev ? pin 1 notch r = 0.20 or 0.35 45 chamfer 3.15 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 3.30 0.05 3.30 0.10 0.45 bsc 0.23 0.05 0.45 bsc de package 16-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1732 rev ?)
lt c2992 44 rev a for more information www.analog.com package description please refer to http://www.linear.com/product/LTC2992#packaging for the most recent package drawings. msop (ms16) 0213 rev a 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev a)
lt c2992 45 rev a for more information www.analog.com information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. revision history rev date description page number a 04/18 corrected data pointers in figure 7 19
lt c2992 46 rev a for more information www.analog.com d16849-0-4/18(a) www.analog.com ? analog devices, inc. 2017-2018 related parts typical application part number description comments lt ? 2940 power and current monitor 4-quadrant multiplication, 5% power accuracy, 4v to 80v operation ltc2941 i 2 c battery gas gauge 2.7v to 5.5v operation, 1% charge accuracy ltc2942 i 2 c battery gas gauge 2.7v to 5.5v operation, 1% charge, voltage and temperature ltc2943 high voltage battery gas gauge 3.6v to 20v operation, 1% charge, voltage, current and temperature ltc2945 wide range i 2 c power monitor 0v to 80v operation, 12-bit adc with 0.75% tue ltc2947 power/energy monitor with integrated sense resistor 30a current range with 9ma offset ltc2990 quad i 2 c temperature, voltage and current monitor 3v to 5.5v operation, 14-bit adc ltc4150 coulomb counter/battery gas gauge 2.7v to 8.5v operation, voltage-to-frequency converter ltc4151 high voltage i 2 c current and voltage monitor 7v to 80v operation, 12-bit resolution with 1.25% tue ltc4215 single channel, hot swap controller with i 2 c monitoring 8-bit adc, adjustable current limit and inrush, 2.9v to 15v operation ltc4222 dual channel, hot swap controller with i 2 c monitoring 10-bit adc, adjustable current limit and inrush, 2.9v to 29v operation ltc4260 positive high voltage hot swap controller with i 2 c monitoring 8-bit adc, adjustable current limit and inrush, 8.5v to 80v operation ltc4261 negative high voltage hot swap controller with i 2 c monitoring 10-bit adc, floating topology, adjustable inrush bidirectional wide range power monitor v dd LTC2992 sdai sdao scl gpio1 gpio2 gpio3 v in 3v to 100v i 2 c interface alert 2992 ta10 sense1 ? sense2 + sense2 ? sense1 + r sense 0.01 0.1f adr0 adr1 gnd intv cc gpio4 board temperature p temperature dataready v out

▲Up To Search▲

Price & Availability of LTC2992

	To Download LTC2992 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .